B<mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML" altimg="si36.svg" display="inline" id="d1e438"><mml:msup><mml:mrow /><mml:mrow><mml:mn>2</mml:mn></mml:mrow></mml:msup></mml:math>N<mml:math xmlns:mml="http://www.w3.org/1998/Math/MathML" altimg="si36.svg" display="inline" id="d1e446"><mml:msup><mml:mrow /><mml:mrow><mml:mn>2</mml:mn></mml:mrow></mml:msup></mml:math>: Resource efficient Bayesian neural network accelerator using Bernoulli sampler on FPGA

A resource efficient hardware accelerator for Bayesian neural network (BNN) named B2N2, Bernoulli random number based accelerator, is proposed. As networks expand their application into risk sensitive domains where mispredictions may cause serious social and economic losses, evaluating the NN’s confidence on its prediction has emerged as a critical concern. Among many uncertainty evaluation methods, BNN provides theoretically grounded way to evaluate of output by treating parameters variables. By exploiting central limit theorem, we propose replace costly Gaussian generators (RNG) with RNG which can be efficiently implemented since possible outcome from distribution binary. We demonstrate that B2N2 Xilinx ZCU104 FPGA board consumes only 465 DSPs 81661 LUTs corresponds 50.9% 14.3% reductions compared Gaussian-BNN (Hirayama et al., 2020) same fair comparison. further compare VIBNN (Cai 2018), shows successfully reduced usages 57.9%, respectively. Owing resources, improved energy efficiency 7.50% 57.5%